1. Field of the Invention
The present invention relates generally to bias circuits. More specifically, the present invention relates to bias startup circuits.
2. Description of the Related Art
Bias circuits are utilized to provide bias voltages or bias currents in a wide variety of integrated circuits. Within an integrated circuit, the bias voltages or currents are utilized in many different circuits to provide proper bias levels for the various transistor circuitry. Generally, a highly accurate and non-temperature dependent circuit such as a band-gap voltage source is utilized to generate a reference bias voltage or current. The reference bias voltage or current may then be provided to additional or secondary bias circuitry to generate a plurality of bias voltages or currents.
The secondary bias circuitry may be utilized to drive operating circuitry that may be high swing or low swing circuitry. In general to drive high swing operating circuitry, the amount of the total power supply voltage consumed by the biasing devices should be relatively low and a relatively large amount of voltage remains so that wider signal voltage variations (i.e. swing) may be obtained from the operating circuitry. Generally, higher swing in the operating circuitry is desirable because it typically results in a higher signal to noise ratio of the operating circuit. A bias circuit for use with high swing operating circuits generally provides outputs relatively close to the voltage rails (as compared to a bias circuit which may only bias a low swing circuit). A bias circuit for biasing a high swing operating circuit may be identified as a high swing bias circuit (which may also be utilized for biasing a low swing operating circuit) and a bias circuit for biasing a low swing operating circuit may be identified as a low swing bias.
For example, FIG. 1C is a prior art bias circuit configured in a cascode manner which may provide outputs (pm, pc, nm, and nc) that may be utilized to bias a high swing circuit. FIG. 1A, however, is a prior art bias circuit configured in a cascode manner which may provide outputs (pm, pc, nm, and nc) that will only bias a low swing circuit. With reference to FIG. 1C, in a circuit with a 2.5 Vdd level and typical transistor Vt and Von values, a high swing bias circuit may provide voltage outputs ranging of 0.75 V, 1.0 V, 1.5 V and 1.75 V at output nodes nm, nc, pc, and pm respectively.
In order to conserve power, it is generally desirable to power down the secondary bias circuitry at times in which the integrated circuit or portions of the integrated circuit are not operating or do not require the bias voltages or currents. After power down, a method to restart or power up the secondary bias circuitry quickly and efficiently is desirable.
FIGS. 1A, 1B and 1C illustrate exemplary prior art bias circuits. For example, FIG. 1A illustrates a low swing cascode bias circuit 10. A current source 100 is provided from a reference bias circuit, such as for example bias circuit based upon a band-gap voltage source circuit. An n-channel cascode transistor 102 and an n-channel mirror transistor 104 are also provided. Four voltage outputs pm, pc, nc, and nm are coupled to transistors 106, 108, 110 and 112 respectively. As used herein the outputs are labeled p for p-channel, n for n-channel, c for cascode and m for mirror.
FIG. 1B illustrates a high swing cascode bias circuit 12 for generating four bias voltages pm, pc, nc, and nm. The non-series connections of transistors 102 and 104 and transistors 106 and 108 provide a higher swing for the bias circuit 12 outputs pm, pc, nc, and nm. Because of the non-series connection of p-channel transistors 106 and 108, additional n-channel transistors 114 and 116 are provided as shown. The bias circuit 12, requires an additional current source 101 to be generated from the reference bias circuit as compared to the circuit of FIG. 1A. This additional current source 101 increases the circuitry within the reference bias circuit and increases the number of routing leads that are required between the reference bias circuit and the bias circuit 12.
FIG. 1C illustrates yet another bias circuit 14. The bias circuit 14 also requires two bias currents to be provided from the reference bias circuit. Thus the bias circuit 14 suffers from some of the same problems as the bias circuit 12 of FIG. 1B. The circuits of FIGS. 1A-1C may be powered down through the use of power down switches 120 which may be closed during power down modes to tie nodes pm and pc to Vdd and nodes nc and nm to ground.
It would be desirable to provide a bias circuit which solves the problems discussed above and others.
In accordance with the present invention, a high swing cascode bias circuit is provided for use within an integrated circuit. The bias circuit utilizes a start up transistor. The use of the start up transistor allows for high swing at the bias circuit outputs even though only one current source is provided from a reference bias circuit. The bias circuit may be powered down in response to a power down control signal. When the bias circuit is activated a plurality of bias signals may be provided to operating circuits of the integrated circuit.